Susitronix, the solution for your complicated bespoke processing systems.
High-Bandwidth ADC & DAC interfacing and timing solutions
Software-Defined Radio
FPGA SoC- and FPGA PCIe- based processing
RADAR, SONAR, LIDAR, and Ultrasound system design
CUDA implementation
Linux kernel and DMA drivers
High-Rate C, C++ coding
We have a large inventory of FPGA development boards and peripherals. Within minutes of an initial consultation, we can be working towards a demonstrator for your project and validation that your concept can be manifested.
left: 32 channel ultrasound front-end with Zynq SoC
Susitronix is well known for it's ability to get your SDR concept working fast! We work with many technologies. Ultimately, a design may rely on LVDS or JESD204 interfacing.
Above: Zynq SoC and E2V 5Gsps low-latency ADC
With many years experience in RADAR systems, Susitronix is well-situated to help get your radar off the ground. We also upgrade legacy systems as shown here
Above: C-band Scatterometer Zero-IF removal and new IF digitization added
Susitronix is a known leader in real-time processing on board FPGAs. Many customers may be finishing the RTL processing algorithm and about to embark on a board design. We can pull a demonstrator together quickly and off-load real-world test data, while assisting in your timing, layout, and IO constraints for your new designs.
Left: 2-channel 3 Gsps ADC, customizable DDC, and DMA architecture with Zynq MPSoC. Below: Kintex Ultrascale with 4-channel 3 Gsps and 10G Ethernet. Below, Left-Lower: MicroZed with modified Hittite 1520 ADC. Below, Left-Upper: ZC706 and optical Ethernet clock-recovery and PTP timing.
Susitronix has extensive simulation methodologies for a given hardware scenario, as well as hardware-in-the-loop.
Above: Loopback of base-band chirp signal to UHF and back on Zynq RFSoC
Susitronix has extensive simulation methodologies for a given hardware scenario, as well as hardware-in-the-loop.
Above: Loopback of base-band chirp signal to UHF and back on Zynq RFSoC
Leverage our experience with FPGA PCIe as Root Complex and storage solutions.
Left: MPSoC with RTL-based PCIe 3.0 and quad-NVMe storage
For more information email john@susitronix.com